# Why should a combinatorial circuit be investigated

## Combinatorial circuit Graycode

### Table of Contents

List of figures

List of tables

1 Introduction

1.1 Introduction to the subject

1.2 Problem and aim of this work

1.3 Structure of the thesis

2. Basics

2.1. Flip flops

2.2. RS flip-flop

2.2.1. JK flip-flop

2.3. Graycode

3rd main part

3.1. Synchronous counter

3.1.1. Truth table

3.1.2. Application equations

3.1.3. Characteristic equations

3.1.4. Linking equations

3.1.5. Circuit diagram

3.2. Combinational circuit binary code / gray code

3.2.1. Truth table

3.2.2. Application equations

3.2.3. Links

3.2.4. Circuit diagram

4. Conclusion

5. Bibliography and sources

### List of figures

Figure 1 Classification of flip-flops

Figure 2 RS flip-flop made of NAND gates and circuit symbol

Figure 3 Structure and circuit symbol of a JK flip-flop

Figure 4 KV diagram for B0, (n + 1)

Figure 5 KV diagram for B1, (n + 1)

Figure 6 KV diagram for B2, (n + 1)

Figure 7 Counter circuit 3-bit synchronous up counter (Logisim)

Figure 8 KV diagram for G

Figure 9 KV diagram for G

Figure 10 KV diagram for G

Figure 11 Combinatorial circuit binary / gray code (Logisim)

### List of tables

Table 1 RS flip-flop truth table

Table 2 Truth table of a JK flip-flop

Table 3 4-bit gray code

Table 4 Truth table of a 3-bit synchronous up counter

Table 5 Truth table binary code / gray code

### 1 Introduction

### 1.1 Introduction to the subject

In this elaboration, the topic of "synchronous counters" is treated as a branch of digital technology. Almost all counters currently in use are binary counters, which are made up of binary components.^{1} These bistable flip-flops are called flip-flops. The basic components used here are JK flip-flops, which are explained in more detail in the basics. A basic distinction is made between asynchronous and synchronous counters for counters (binary counters). The difference between the two lies in the control of the individual flip-flops. With an asynchronous counter, the subsequent flip-flop is controlled by the output of the upstream flip-flop. The flip-flops therefore do not switch at the same time, but one after the other. This can lead to malfunctions, especially at high counting frequencies. In order to avoid the problem of the switching delay, each trigger stage must be controlled by a common clock signal. This is the basic structure of a synchronous counter.

### 1.2 Problem and aim of this work

The problem and therefore also the main goal of this thesis is the construction of a synchronous 0: 7 counter with the help of JK flip-flops, which then generates the associated gray code by creating a combinatorial circuit from the sequence of the counter.

The challenge with synchronous counters lies in the calculation of the structure and the linkage of the flip-flops, for which there are different methods.

In order to achieve the main goal of this elaboration, a five-step calculation process is used, from which the individual modal goals can be seen.

The calculation method used here is in the following steps^{2} sub-divides:

**1.)** Deriving the KV diagrams to simplify the setup equations**2.)** Determination of the characteristic equations of the flip-flops**3.)** Implementation of the settlement procedure**4.)** Creation of the circuit according to the logic equations

### 1.3 Structure of the thesis

At the beginning of this elaboration, the relevant basics for this task are discussed.

The basics deal with the structure and function of flip-flops and the general structure of the Gray code with any length.

The concept part consists on the one hand of the construction of a synchronous 0: 7 counter which is set up with the help of JK flip-flops.

The second part deals with the creation of a combinational circuit that generates the associated Gray code for the sequence of the counter.

The results achieved are summarized again in the final analysis and evaluated with regard to the goals.

### 2. Basics

### 2.1. Flip flops

A bistable multivibrator is called a flip-flop. It is an electronic circuit which can assume two stable states and can therefore store a data volume of one bit.^{3} This makes the flip-flop an indispensable component in digital technology.

However, there are differences in the conditions when changing from one stable state to another.^{4} The classification of flip-flops is therefore carried out on the basis of the clock dependency and is shown in the following figure.

Figure not included in this excerpt

Figure 1 Classification of flip-flops

Clock dependency means that, for example, a state 1 can only take effect at an input if a state 1 is also present at the clock input. This type of control is called clock state control.

The number of possible flip-flop circuits is very large and would by far exceed this basic consideration.

Therefore, the most important flip-flops are listed below, the RS flip-flop is presented and the JK flip-flop relevant for this work is examined more closely:

- RS flip-flop (also clock status and clock edge controlled)

- D flip-flop

- JK flip-flop

- JK master-slave flip-flop

### 2.2. RS flip-flop

The structure of an RS flip-flop can be implemented using NAND or NOR gates.^{5} It is the flip-flop with the least amount of circuitry and is considered to be the simplest flip-flop.

The hallmark of this type of flip-flop are the cross-coupled inverted gates. Figure 2 shows an RS flip-flop consisting of NAND gates, with the inputs S (set) and R (reset).

Figure not included in this excerpt

Figure 2 RS flip-flop made of NAND gates and circuit symbol

Figure not included in this excerpt

Table 1 Truth table RS flip-flop

As can be seen in Table 1, even short interference pulses at the inputs can lead to incorrect setting and resetting. This is prevented by different measures, e.g. with D and JK flip-flops.

#### 2.2.1. JK flip-flop

The JK flip-flop is named after its inventor Jack Kilby. In principle, this is an edge-controlled RS flip-flop with two integrated AND gates, which is shown in Figure 3. Due to the feedback of the outputs Q and mapping not included in this reading sample, the impermissible state S = R = 1 is prevented.

Figure not included in this excerpt

Figure 3 Structure and circuit symbol of a JK flip-flop

The JK flip-flop only switches on a rising or falling edge at C, not in the entire range C = 1. The state J = K = C = 1 causes the JK flip-flop to switch the output states back and forth, which is referred to as toggling. The JK flip-flop inverts its previous state, it works as a frequency divider (binary divider).^{6} Table 2 shows the individual functions for different input assignments. The variable n denotes the dependence of J and K, the variable x that of the previous state.

Figure not included in this excerpt

Table 2 Truth table of a JK flip-flop

### 2.3. Graycode

The Gray code is a one-step code in which two neighboring numbers must not differ in more than one bit. This is necessary if the point in time of the switchover cannot be precisely adhered to.^{7}

In contrast to the binary code, no errors can occur here with a parallel readout. The readout errors are caused by different transit times of the signal bits, which therefore arrive at the evaluation unit with a delay of a few hundred nanoseconds, which can lead to undesired intermediate states.

The Gray code is mainly used for controls that, for example, scan the coding of control disks.^{8} So that the Gray code remains cyclical, it must always extend to all tetrads, otherwise more than just one bit can change (e.g. from 3 (10) = 0011 to 0 (10) = 0000).

Figure not included in this excerpt

Table 3 4-bit gray code

The general structure of the Gray code in any length follows the scheme in Table 3. Each position to the left receives twice the number of zeros and ones of the preceding ones, starting with the zeros.

### 3rd main part

### 3.1. Synchronous counter

The implementation of a synchronous counter is carried out in the following using a five-digit calculation. 3 bits are required to count 0: 7. This is referred to as a 3-bit synchronous up counter.

#### 3.1.1. Truth table

The truth table, shown in Table 4, serves on the one hand to provide an overview of the counter readings before (Zn) and after a clock signal (Zn + 1) and on the other hand as an aid to the graphic implementation of the KV diagrams.

Figure not included in this excerpt

Table 4 Truth table of a 3-bit synchronous up counter

#### 3.1.2. Application equations

In order to obtain the respective DNF, the Karnaugh-Veitch diagram is used below. Other possibilities would be Boolean algebra or the Quine-McCluskey algorithm. In principle, the KV diagram only represents a different arrangement of the truth table.^{9}

**[...]**

^{1} See BEUTH (2006), p. 317

^{2} See BEUTH (2006), p. 350

^{3} See BEUTH (2006), p. 184

^{4} See Woitowitz / Urbanski / Gehrke (2011), p. 174

^{5} See Fricke (2009), p. 78

^{6} See Kories / Schmidt-Walter (2006), p. 503

^{7} See Fricke (2009, p. 11

^{8} See BEUTH (2006), p. 261

^{9} See Woitowitz / Urbanski / Gehrke (2011), p. 42

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